1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to a large-scale semiconductor integrated circuit, e.g., a microcomputer, having a standby function of stopping the entire operation to set a low power consumption state and incorporating decoders for a ROM, a RAM, a selector, and the like.
2. Description of the Prior Art
In recent years, as the micropatterning technique in the semiconductor integrated circuit manufacturing technology progresses, the thickness of the gate oxide film becomes extremely thin, and the leakage current defect caused by breakdown of the gate oxide film fabricated during manufacture poses a problem. This problem is particularly conspicuous in a state wherein the entire operation of a semiconductor integrated circuit, e.g., a microcomputer is stopped by a signal input from an external terminal or a program that aims at reducing the power consumption (this state will be referred to as the standby mode hereinafter). The larger the circuit scale, the more likely that a defect occurs.
The general arrangement of a microcomputer having the standby mode will be described with reference to the block diagram shown in FIG. 1.
In the normal operation, this microcomputer supplies a system clock SCK generated by an oscillator 12 to a CPU 11 and peripheral units 13a to 13d including a serial interface, a ROM, a RAM, a timer, and the like, so that the entire microcomputer operates. When a request for transition to the standby mode occurs, a standby signal STBY serving as a control signal which sets the standby mode is generated in the CPU 11 and is input to the oscillator 12. Upon reception of the standby signal STBY, the oscillator 12 stops oscillation, and stops supplying the system clock SCK to the CPU 11 and peripheral units 13a to 13d, thereby stopping the entire operation of the microcomputer.
The factor that causes the leakage current to pose a problem particularly in the standby mode will be explained. FIG. 2 is a sectional view of an inverter circuit portion included in a CMOS-type semiconductor integrated circuit, e.g., a microcomputer. A gate Gn, a source Sn, and a drain Dn constitute an n-channel type transistor (to be referred to as an n-channel transistor hereinafter), and a gate Gp, a source Sp, and a drain Dp constitute a p-channel type transistor (to be referred to as a p-channel transistor hereinafter).
In the manufacturing process, when gate oxide films GOn and GOp of the n- and p-channel transistors are broken, the electrical insulating properties decrease, and a leakage current flows between the gate Gn of the n-channel transistor and a group of the source Sn, drain Dn, p-well 102 and a p-type substrate 101, and between the gate Gp of the p-channel transistor and a group of the source Sp, drain Dp, an n-well 103 and the p-type substrate 101. In order to prevent supply of defective products having such a leakage current defect in the standby mode to the market, usually, data "0" and "1" are written in all the memory elements, e.g., a RAM cell, a register, and the like. The current obtained with each of data "0" and "1" in the standby mode is measured twice. Thereafter, only the non-defective products are shipped to the market.
An output from which one of decoders for a ROM, a RAM, a selector, and the like goes active in the standby mode is indefinite. In order to prevent supply of defective products having a leakage current defect to the market, outputs from the respective decoders must be set at low level one by one, and the resultant current must be measured. For this reason, the larger the decoder scale becomes, the longer the time required for measuring the leakage current. This will be explained using a 64-kbyte mask ROM (the first example of a conventional semiconductor integrated circuit) with reference to FIG. 3 showing the arrangement of this mask ROM.
A row decoder 2x decodes address data A6 to A15 and outputs them onto word lines WL1 to WLm of a memory cell array 1x. Namely, one of the 1,024 word lines WL1 to WLm (m=1,024) of the 64-kbyte memory cell array 1x is selected by the 10 upper bits of 16-bit address data A0 to A15, and is set at active level (selection level).
A column decoder 14 decodes the address data A2 to A5 of the 16-bit address data A0 to A15, and outputs 16 column selection signals YS1 to YSk (k=16) to a column selector 15. 512 bit lines BL11 to BL1k, . . . and BLn1 to BLnk (n=32) have been input to the column selector 15 from the memory cell array 1x. One bit line is selected from each of 32 groups obtained by dividing the 512 bit lines into groups each including 16 bit lines (16.times.32=512) in accordance with which one of the column selection signals YS1 to YSk input from the column decoder 14 is at "1", and data corresponding to the selected bit lines are output to a sense amplifier 16. For example, when the column selection signal YS1 is at "1", the bit lines BL11 to BLn1 respectively selected from the respective groups each including the 16 bit lines are selected, and data are output to the sense amplifier 16. Namely, the 4 lower bits, excluding the 2 lowest bits A0 and A1 (the 2 lowest bits A0 and A1 are required only when a data read operation is performed in units of bytes, and are not used in this example since the data read operation is performed in units of 32 bits), of the 16-bit address data A0 to A15 select 32 bit lines among the 512 bit lines BL11 to BL1k, . . . and BLn1 to BLnk of the memory cell array 1x.
The sense amplifier 16 detects and amplifies the data of the address on the memory cell array 1x which is designated by the 14-bit address data A2 to A15 in this manner, converts it to a logical value "0" or "1", and outputs it in the form of 32-bit output data DO1 to DOn.
In the mask ROM having this arrangement, when the contents of the address data A2 to A15 change depending on the timing of transition to the standby mode, the contents of one of 1,024 word lines WL1 to WLm selected by the row decoder 2x and 32 of the 512 bit lines BL11 to BL1k, . . . and BLn1 to BLnk selected by the 16 column selection signals YS1 to YSk of the column decoder 14 change. In order to completely detect a leakage current defect in the memory cell array 1x in the standby mode, all possible cases of the address data A2 to A15 which set the standby mode must be assumed. In other words, the leakage current must be measured by setting all of the 1,024 word lines WL1 to WLn and the column selection signals YS1 to YSk at active level in the standby mode. The word lines WL1 to WLm can be set at active level only one at a time. For the measurement of the leakage current, the address data A2 to A15, with which a predetermined one of the 16 column selection signals YS1 to YSk is selected each time the word lines WL1 to WLm are selected one by one, must be set 1,024 times. If one current measurement operation takes 1 msec, a total time equal to or longer than 1 sec is needed. In this manner, the larger the scale and number of decoders for circuits, e.g., a ROM, a RAM, a selector, and the like, the longer the time required for measurement of the leakage current in the standby mode is.
Japanese Unexamined Patent Publication No. 6-35743 discloses an example wherein the leakage current is detected by setting all the word lines at active level and all the bit lines at inactive level by a control signal. FIG. 4 is a circuit diagram of a dynamic ROM (the second example of the conventional semiconductor integrated circuit) fabricated by referring to Japanese Unexamined Patent Publication No. 6-35743.
In this dynamic ROM, in the normal operation, a control signal CNT is at low level, and all word lines WL1 to WLM and all bit lines BL1 to BLN are precharged or discharged with a word line precharge/discharge signal WP.multidot.D and a bit line precharge/discharge signal BP.multidot.D, respectively, to access an address of a memory cell array 1y which is designated by address data A0 to Aj.
When measuring the leakage current, the control signal CNT is set at high level, and all the word lines WL1 to WLM are set at high level, which is precharge level, by a control circuit 10 and precharge transistors Q21 included in a decoder 2y and all the bit lines BL1 to BLN are set at low level, which is discharge level, by the control circuit 10 and discharge transistors Q12. Then, unlike in the first example, the word lines need not be sequentially set at high level one by one, and the leakage current can be detected with a smaller number of operation times. Of the word and bit lines, one is set at high level while the other is set at low level so that the leakage current of the gate oxide film can be detected more reliably.
FIG. 5 shows a typical example (the third example of the conventional semiconductor integrated circuit) in which the technique of measuring the leakage current by setting all the word lines at high level is applied to a static ROM (an example for explaining the basic principle in which four word lines are provided).
This semiconductor integrated circuit has a row decoder 2, a memory cell array 1, and a decoder output control circuit 9. The row decoder 2 has inverters IV21 and IV22, and AND gates G21 to G24, and outputs a signal that sets one of word lines WL1 to WL4 at high level, which is selection level (active level), in accordance with address data A1 and A2. The memory cell array 1 outputs data, which is stored in a memory cell connected to the word line at selection level, to bit lines BL1 to BLm. The decoder output control circuit 9 has OR gates G91 to G94, transmits an output signal from the row decoder 2 to a corresponding word line when a control signal CNT is at low level, sets all the word lines WL1 to W14 at high level when the control signal CNT is at high level.
In this semiconductor integrated circuit as well, since the control signal smaller number of operation times without setting the word lines WL1 to WL4 at high level one by one.
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FIG. 6 is a circuit diagram showing an example of another semiconductor integrated circuit (the fourth example) having decoders.
This semiconductor integrated circuit has a frequency divider 4, a decoder 5, and a selector 6. The frequency divider 4 frequency-divides a system clock SCK into three D clock signals DCK1 to DCK3 having different periods. The decoder 5 has inverters IV51 and IV52 and NOR gates G51 to G53, and decodes clock selection control signals SC1 and SC2 and outputs clock selection signals SL1 to SL3. The selector 6 has AND gates G61 to G63 and a NOR gate G64, and selects one of the clock signals DCK1 to DCK3 frequency-divided in accordance with the clock selection signals SL1 to SL3 and supplies the selected signal to an internal processing unit 7 as an internal clock ICK.
In this semiconductor integrated circuit, when the clock selection control signals SC1 and SC2 are (0, 0), the internal clock ICK is not supplied. When the clock selection control signals SC1 and SC2 are (0, 1), (1, 0), and (1, 1), the clock signals DCK1, DCK2, and DCK3 are selected, respectively, and the selected signal is supplied as the internal clock ICK.
In this semiconductor integrated circuit as well, the contents of the clock selection control signals SC1 and SC2 change depending on the timing of transition to the standby mode. Accordingly, in detection of the leakage current in the standby mode, current measurement is performed in all states of the clock selection control signals SC1 and SC2.
In the conventional semiconductor integrated circuits described above, in the first and fourth examples, the contents of signals (A6 to A15, SC1, SC2) input to the row decoder 2x, the decoder 5, and the like change depending on the timing of transition to the standby mode. For detection of the leakage current in the standby mode, current measurement must be performed in all states of the signals input to the row decoder 2x, the decoder 5, and the like, leading to an increase in detection of the leakage current. In the second and third examples in which all the word lines are set at active level with the control signal CNT, logic gates must be formed to correspond to all the output signals from the row decoder 2y or 2 or all the word lines. Accordingly, the circuit scale increases. A circuit for generating the control signal CNT is necessary, increasing the circuit scale. Also, a leakage current of the row decoder, the decoder, or the like itself cannot be detected.